This invention relates to semiconductor integrated circuit devices including dynamic random access memories having voltage boosting circuits built in.
An example of a dynamic RAM that incorporates pumping circuitry to generate a substrate voltage and a boosted voltage is disclosed in Japanese Patent Application Provisional Publication No. 214669/91. In this application, the pumping circuitry (charge pump circuit) which generates a substrate voltage and a boosted voltage consists of a main circuit and a sub-circuit, where the sub-circuit has only a small current capability to compensate for leakage current and the like.
In recent years, more and more semiconductor integrated circuits, such as memories and microprocessors, incorporate positive or negative charge pump circuits in their chips in order to provide a user-friendly single external power supply or enhance the performance of the devices. However, in address selective MOSFETs which constitute memory cells in dynamic RAMS, it is difficult to decrease the threshold voltage, because a decrease in threshold voltage means an increase in sub-threshold current in accordance with the rule of scaling, which reduces the information retention time. The voltage to be generated in the charge pump circuit, or the selection level in said address selective MOSFETs, cannot be lowered in proportion to the device size even if the device is very small, but will be nearly the same level as the device withstand voltage. Thus, it is an important objective to ensure the reliability of these devices.
FIG. 10 shows a voltage boosting circuit conceived prior to this invention. In this circuit, after capacitors CB1, CB2 and CB4 are precharged to the level of VDD, nodes N1 and N2 are brought to VDD. Here, the charge in capacitor CB2 passes through MOSFET M8 to bring the drain and source sides of capacitor CB4 to 2VDD. Therefore, the potential on the gate side of capacitor CB4 becomes 3VDD. Since in this circuit the gate voltage of the rectifier MOSFET M1 goes up to 3VDD, the current capability can be increased. If a device made through the 0.3 xcexcm process is used, VCH is 4.0 V with VDD=2.9 V, VTN(M1)=1 V, W/L(M1)=75 xcexcm/1 xcexcm, load current=2 mA, which satisfies the voltage requirement of 3.8 V for fully writing into the memory cells. However, a maximum of 2VDD is applied to MOSFET M7, which voltage exceeds the device gate withstand voltage. Usually, the permissible electric field for a gate oxide film is below 5 MV/cm. In this circuit, however, if tox=8 nm, the gate-source voltage of the MOSFET M7 becomes 7.2 V and the electric field becomes 9 MV/cm at VDD=3.7 V, which exceeds the permissible voltage range.
The object of this invention is to provide a semiconductor integrated circuit device which has an internal voltage generating circuit to reduce the voltage applied to devices while generating a voltage which is two or more times higher than the operating voltage and ensure the device reliability. This object and other objects of the invention and its novel features will be more clearly understood from the following specification and the attached drawings.
Typical embodiments of this invention are briefly summarized below. In the charge pump circuit which is driven by the supply voltage VDD, a MOSFET, having a maximum of 2VDD or a similar level voltage applied between the drain and source thereof, is connected in series with an equivalent conduction type MOSFET, which has its gate supplied with VDxe2x88x92VDD, or a potential VDD lower than VD (drain potential before the connection). The above-said gate potential is obtained directly from a node in the above charge pump circuit generating voltage pulses synchronized with the voltage between the drain and source of that MOSFET or through another rectifier device branched via a capacitor from the node.